1. Field of the Invention
The present invention relates to a semiconductor circuit and, more particularly, to a semiconductor circuit to correct degradation in duty cycle of a differential signal to be output.
2. Description of Related Art
In recent years, current mode logic (CML) has been attracting much attention as a high-speed signal transmission system. In the CML, a differential signal transmission system is employed to transmit signals. Moreover, in the CML, a signal level having a small amplitude (hereinafter, referred to as “CML level”) is used, and in an internal circuit to which signals are transmitted, a signal level having a large amplitude (hereinafter, referred to as “CMOS level”) in a range from a power supply voltage to a ground voltage is used.
FIG. 18 shows a schematic diagram of a circuit 1800 receiving differential clock signals that are small signals such as the CML level, to convert the differential clock signals into differential clock signals having a large amplitude such as the CMOS level to be distributed. As shown in FIG. 18, multiple stages of differential amplifiers 1801 and 1802 first amplify differential clock signals IT and IB that are small signals of the CML level, and then output differential clock signals OT and OB that are converted into signals of the CMOS level. Hereinafter, the differential clock signals IT and IB are abbreviated as IT/IB and the differential clock signals OT and OB are also abbreviated as OT/OB. The same is applied to other differential signals.
As the differential amplifiers 1801 and 1802 shown in FIG. 18, there is used a circuit disclosed in Japanese Patent No. 7-16158. Examples of the circuit include a differential amplifier 1900 as shown in FIG. 19. The differential amplifier 1900 includes NMOS transistors N1901a and N1901b, NMOS transistors N1902a and N1902b, and PMOS transistors P1903a and P1903b. In the differential amplifier 1900 as shown in FIG. 19, when the differential signals IT/IB to be input have different offsets, there arises a problem in that offset components are also amplified, with the result that the degradation in duty cycle is increased.
As shown in FIG. 20, as a countermeasure against the degradation in duty cycle, there is provided a differential amplifier 2000 disclosed in Japanese Unexamined Patent Application Publication No. 2007-60069. The differential amplifier 2000 is constituted by adding PMOS transistors P2001a and P2001b, NMOS transistors N2002a and N2002b, and a transfer gate 2003 to the differential amplifier 1900.
The solid line of FIG. 21 represents a frequency characteristic of the differential amplifier 2000, and the dashed line of FIG. 21 represents a frequency characteristic of the differential amplifier 1900. As apparent from the frequency characteristics shown in FIG. 21, the differential amplifier 2000 suppresses the amplitude of a low-frequency component and amplifies the amplitude of a predetermined high-frequency component. Consideration is given to a case where the input differential signals IT/IB are input to the differential amplifier 2000 as shown in FIG. 22.
The input differential signals IT/IB shown in FIG. 22 have an amplitude Y1 and a difference in offset voltage of X1. In this case, even when the amplitude of both the input differential signals IT/IB is Y1, the duty cycle of the differential signals is, for example, 60:40, whereby symmetry is lowered. In this case, when the input differential signals IT/IB are input to the differential amplifier 2000, the differential amplifier 2000 suppresses the amplitude of the low-frequency component and amplifies the amplitude of the predetermined high-frequency component, thereby suppressing an offset voltage component of each of the input differential signals IT/IB and amplifying the amplitude of a signal component having the amplitude Y1. As a result, as shown in FIG. 23, the differential amplifier 2000 outputs output differential signals OT/OB having an amplitude of Y2 and a difference in offset voltage of X2. The degradation in duty cycle of the output differential signals OT/OB is improved, and the duty cycle is about 50:50.
However, the correction of the degradation in duty cycle by the differential amplifier 2000 is effective only for the input differential signals IT/IB input to input terminals IT and IB of the differential amplifier 2000. In other words, it is impossible to prevent the degradation in duty cycle of the output differential clock signals due to relative process variations among transistors constituting the differential amplifier 2000 itself, imbalance in parasitic capacitance and parasitic resistance of wires of the differential amplifier 2000, and the like. Further, it is impossible to obtain the effect of correcting the degradation in duty cycle of the differential signals caused by relative variations among transistors constituting the differential amplifier 2000 and subsequent circuits.
Further, Japanese Unexamined Patent Application Publication No. 11-274902 discloses a technique in which a low-pass filter is connected to a differential output of a differential receiver and a difference in output of the low-pass filter is amplified to be fed back to an input of the differential receiver, thereby correcting the duty cycle. In the technique, however, if elements such as transistors constituting a correction differential amplifier vary, there arises a problem in that an input offset cannot be compensated and the duty cycle of a differential signal to be output is degraded.